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Daniel Saab

Associate Professor, Department of Electrical, Computer and Systems Engineering
Models and simulates digital systems, and verifies integrated circuit designs
Office: 519B Glennan
Phone Number: (216) 368-2494

Research Interests

• Modelling and Simulation of Digital Systems<br>• Automatic Test Pattern Generation (ATPG) and Design For Testability<br>• Formal Verification<br>• Reconfigurable Computing and CAD Algorithms<br>• Modeling and circuit simulation of Nano-Electro-Mechanical Switches (NEMS)<br>Verification is a critical step in the Integrated Circuit (IC) design process. In order to verify a design, a set of assertions based on the design, is generated. The design is checked, either using simulation or formal tools, to make sure that the design does not violate any of the generated assertions. If any of the assertions is violated, then a design bug is detected. The quality of the verification is directly connected to the set of assertions and how much of the design functionality they cover. In this research, we develop methods to generate a set of high-quality design assertions. Recently, we develop a method based on the design description and on Automatic Test Pattern Generation (ATPG). This method generates design assertions that cover 100% of the design input space and could span multiple clock cycles. Using this method, we generated properties/assertions for a USB2.0 model from OpenCores. The generated assertions are compact and provide 100% input space coverage of each target node.<br>In Nano-Electro-Mechanical research, we proposed a new innovative Nano Electro Mechanical switch (NEMS). The NEMS has virtually zero leakage current, 1-3V operation voltage, 1-10ns switching time and small footprint. In addition to acting as a relay, these NEMS enable the implementation of basic two inputs logic gates using a single device instead of four or more traditional switches. . To evaluate NEMS design, we developed an accurate NEMS SPICE circuit simulation model which enables the measuring of NEMS timing and power requirement. Based on the model and the device fabrication data, we show that NEMS circuit show significant improvement over CMOS technology counterpart (using 65nm and 45 nm technology). In addition, the NEMS switch can be configured to implement any 2-input logic gates (AND, OR, NAND, NOR, XOR, XNOR, NOT) on a single structure. We showed that these devices can be used to

Teaching Interests

Since I joined this university, I have taught courses at the graduate and undergraduate levels. These courses are in computer engineering, VLSI design, VHDL, Verilog, Switching Theory, CAD. In addition to my regular teaching loads, I have been very active in directing Masters and Ph.D. theses.


Han, S., Saab, D. G., & Tabib-Azar, M. (2018). Design, Modeling, and Simulation of a New Nanoelectromechanical Switch for Low-Power Applications. IEEE Transactions on Electron Devices, 65 (8), 3438-3446.