EECS Spring 2014 Department Seminar

Rani S. Ghaida
Rethinking Technology Development: A Virtual Design House
Glennan 313
April 29, 2014

Semiconductor technologists and circuit designers alike constantly find themselves in a dilemma of choice. For scaling to every new technology node, they must decide on an overwhelmingly large number of alternatives: fabrication technology, layout methodologies and constraints, circuit styles, interconnect stacks, standard-cell library schemes, and device architecture. Making informed technological decisions requires accurate projection of their design impact.

Rethinking technology development, this talk presents a computational approach and an infrastructure for the systematic assessment of technological choices. The infrastructure acts as a “virtual design house” that, given the technology specifications under consideration, combines algorithmic methods to create a layout estimate and approximation models to evaluate key design-quality metrics of area, delay, variability, and yield. The evaluation is performed with high fidelity and the entire procedure is completed in minutes, as opposed to months with traditional methods. This speedup radically changes the way technology is defined and optimized. It allows a wide range of technological choices to be explored, thereby unfolding new combinations that are more beneficial. Additionally, this computational technology optimization only requires easy-to-extrapolate manufacturing parameters, which allows its application at early stages of technology development before significant investment in R&D and design enablement had been made. The infrastructure is particularly beneficial for designers as means to avoid unforeseen effects of future technologies and for technology developers as means to assess alternative technologies from the perspective of improving key circuit-design metrics. Furthermore, researchers across the spectrum of microelectronics – process/technology developers and circuit/system designers – can use the infrastructure as a testing platform to supplement theoretical studies with immediate examination of the design impact of choices and innovations they devise. The talk closes with a brief description of some of the biggest challenges and opportunities of future IC design and manufacturing as well as means to address them.


Dr. Rani Ghaida is a Principal Engineer at GlobalFoundries in the Technology Development Division in Silicon Valley. He has a PhD in Electrical Engineering from UCLA. During his PhD studies, he was on two internships at IBM Research, one at Austin Research Lab and another at T. J. Watson Research Center. His research work has been primarily focused on the development of computational techniques and mathematical models for exploring, defining, optimizing, and enabling semiconductor technologies in a digital design context. His work has been used and acquired by some of the leading semiconductor companies spanning various industries: integrated device manufacturing, foundry, research, and electronic design automation. Dr. Ghaida has published 20 technical papers in peer-reviewed conferences and refereed journals and has 4 granted US patents and 4 filed. He is the recipient of the 2012 Outstanding PhD Dissertation Award from the European Design and Automation Association (EDAA) and a number of other awards, most notably the IBM Invention Achievement Plateau Award and the SRC Inventor Recognition Award.